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STK14EC16 1 jan, 2008 document control #ml0061 rev 1.1 this is a product in development that has fixed tar- get specifications that are subject to change pend- ing characterization results. simtek confidential & proprietary preliminary features ? 15, 25, 45 ns read access and r/w cycle time ? unlimited read/write endurance ? automatic non-volatile store on power loss ? non-volatile store under hardware or software control ? automatic recall to sram on power up ? unlimited recall cycles ? 200k store endurance ? 20-year non-volatile data retention ? single 3.0v +20%, -10% operation ? commercial, industrial temperatures ? 44-pin or 54-pin 400-mil tsopii packages (rohs- compliant) ? 48-ball fine pitch ball grid array (fbga) description the simtek STK14EC16 is a 4mb fast static ram with a non-volatile quantum trap storage element included with each memory cell. the sram provides the fast access & cycle times, ease of use and unlimited read & write endurance of a normal sram. data transfers automatically to the non-volatile stor - age cells when power loss is detected (the store operation). on power up, data is automatically restored to the sram (the recall operation). both store and recall operations are also available under software control. the simtek nvsram is the highest performance, most reliable non-volatile memory available. block diagram eeprom array 2048 x 2048 recall store/ recall control hsb power control store sram array 2048 x 2048 input buf fers column i/o dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 dq 8 dq 9 dq 10 dq 11 dq 12 dq 13 dq 14 dq 15 g w e lb a0 - a17 software detect row decoder a 0 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 17 a 1 column decoder a 9 a 10 a 11 a 12 a 13 a 14 a 15 a 16 pachuco boys v cc v cap ub 256kx16 autostore nvsram
2 simtek confidential jan, 2008 document control #ml0061 rev 1.1 STK14EC16 preliminary operating mode e hsb w g lb ub dq0-dq7 dq8-dq15 standby/not selected h h x x x x high-z high-z internal read l h h h x x high-z high-z l h x x h h high-z high-z lower byte read l h h l l h data outputs low-z high-z upper byte read l h h l h l high-z data outputs low-z word read l h h l l l data outputs low-z data outputs low-z lower byte write l h l x l h data inputs high-z high-z upper byte write l h l x h l high-z data inputs high-z word write l h l x l l data inputs high-z data inputs high-z truth table for sram operations
STK14EC16 3 simtek confidential jan, 2008 document control #ml0061 rev 1.1 preliminary pin descriptions pin name i/o description a 17 -a 0 input address: the 18 address inputs select one of 262,144 words in the nvsram array dq 15 -dq 0 i/o data: bi-directional 16-bit data bus for accessing the nvsram e input chip enable: the active low e input selects the device lb input byte write select input: controls dq7-dq0 (unselected by te will not write or read). ub input byte write select input: controls dq15-dq8 (unselected byte will not write or read). w input write enable: the active low w enables data on the dq pins to be written to the address location latched by the falling edge of e g input output enable: the active low g input enables the data output buffers during read cycles. de-asserting g high causes the dq pins to tri-state. v cc power supply power: 3.0v +20%, -10% hsb i/o hardware store busy : when low this output indicates a store is in progress (also low during power up while busy). when pulled low external to the chip, it will initiate a nonvolatile store operation. a weak pull up resistor keeps this pin high if not co nnected. (connection optional). v cap power supply autostore capacitor: supplies power to the nvsram during a power loss to store data from sram to nonvolatile storag e ele- ments. v ss power supply ground nc no connect this pin is not connected to the die. (do not connect in design; reserved for future use) 44-pin tsop-ii (see full mechanical drawings on pages 18 ? 20) 54-pin tsop-ii 48-ball fbga v ss a 2 a 3 a 4 a 5 dq 0 dq 1 v cc v cap dq 2 dq 3 a 6 a 7 a 8 a 1 a 17 a 16 a 15 a 14 a 13 dq 7 dq 6 v ss v cc dq 5 dq 4 a 12 a 11 a 9 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 a 0 a 10 e w dq 8 dq 9 dq 10 dq 11 g dq 12 dq 13 dq 14 dq 15 ub lb v ss a 0 a 1 a 2 a 3 a 4 a 5 dq 0 dq 1 v cc v cap dq 2 dq 3 a 6 a 7 a 8 nc nc a 17 a 16 a 15 a 14 a 13 g dq 7 dq 6 v ss v cc dq 5 dq 4 hsb a 12 a 11 a 9 nc nc nc 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 nc a 10 e nc nc 23 24 25 26 27 w 54 53 52 51 50 49 48 47 46 45 ub lb dq 15 dq 14 dq 13 dq 12 dq 11 dq 10 dq 9 dq 8 nc lb g a 0 a 1 a 2 nc dq 8 ub a 3 a 4 e dq 0 dq 9 dq 10 a 5 a 6 dq 1 dq 2 v ss dq 11 a 17 a 7 dq 3 v cc v cc dq 12 v cap a 16 dq 4 v ss dq 14 dq 13 a 14 a 15 dq 5 dq 6 dq 15 hsb a 12 a 13 w dq 7 nc a 8 a 9 a 10 a 11 nc 1 2 3 4 5 6 a b c d e f g h (top) (top) (top)
4 simtek confidential jan, 2008 document control #ml0061 rev 1.1 STK14EC16 preliminary absolute maximum ratings a voltage on input relative to ground . . . . . . . . . . . . . ?0.5v to 4.1v voltage on input relative to v ss . . . . . . . . . . ?0.5v to (v cc + 0.5v) voltage on dq 0-7 or hsb . . . . . . . . . . . . . . . . ?0.5v to (v cc + 0.5v) temperature under bias. . . . . . . . . . . . . . . . . . . . . .?55 c to 125 c junction temperature . . . . . . . . . . . . . . . . . . . . . . .?55 c to 140 c storage temperature . . . . . . . . . . . . . . . . . . . . . . . .?65 c to 150 c power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1w dc output current (1 output at a time, 1s duration) . . . . . . . 15ma note a: stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at con - ditions above those indicated in t he operational sections of this specification is not implied. exposure to absolute maximum rat - ing conditions for extended periods may affect reliability. dc characteristics (v cc = 2.7v-3.6v) note: the hsb pin has i out =-10 ua for v oh of 2.4 v. this parameter is characterized but not tested. symbol parameter commercial industrial units notes min max min max i cc 1 average v cc current 70 65 50 75 70 52 ma ma ma t avav = 15ns t avav = 25ns t avav = 45ns dependent on output loading and cycle rate. values obtained without output loads. i cc 2 average v cc current during store 6 6 ma all inputs don?t care, v cc = max average current for duration of store cycle (t store ) i cc 3 average v cc current at t avav = 200ns 3v, 25c, typical 26 26 ma w (v cc ? 0.2v) all other inputs cycling at cmos levels dependent on output loading and cycle rate. values obtained without output loads. i cc 4 average v cap current during auto store cycle 6 6 ma all inputs don?t care average current for duration of store cycle (t store ) i sb v cc standby current (standby, stable cmos levels) 3 3 ma e ( v cc -0.2v) all others v in 0.2v or (v cc -0.2v) standby current level after nonvolatile cycle complete i ilk input leakage current 1 1 a v cc = max v in = v ss to v cc i olk off-state output leakage current 1 1 a v cc = max v in = v ss to v cc , e or g v ih v ih input logic ?1? voltage 2.0 v cc + 0.5 2.0 v cc + 0.5 v all inputs v il input logic ?0? voltage v ss ?0.5 0.8 v ss ?0.5 0.8 v all inputs v oh output logic ?1? voltage 2.4 2.4 v i out = ? 2ma (except hsb ) v ol output logic ?0? voltage 0.4 0.4 v i out = 4ma t a operating temperature 0 70 ?40 85 c v cc operating voltage 2.7 3.6 2.7 3.6 v 3.3v nominal v cap storage capacitance 61 134 61 180 f between v cap pin and v ss , 5v rated (nom. 68 f to 150 f +20%, - 10%) nv c nonvolatile store operations 200 200 k data r data retention 20 20 years @ 55 deg c tf (tsop-ii 44) package thermal characteristics jc tbd; ja tbd [0fpm], tbd [200fpm], tbd c/w [500fpm]. uf (tsop-ii 54) package thermal characteristics jc tbd; ja tbd [0fpm], tbd [200fpm], tbd c/w [500fpm]. bf (fbga48) package thermal characteristics jc tbd c/w; ja tbd [0fpm], tbd [200fpm], tbd c/w [500fpm].
STK14EC16 5 simtek confidential jan, 2008 document control #ml0061 rev 1.1 preliminary ac test conditions capacitance b (t a = 25 c, f = 1.0mhz) note b: these parameters are guaranteed but not tested. input pulse levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0v to 3v input rise and fall times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5ns input and output timing reference levels . . . . . . . . . . . . . . . 1.5v output load . . . . . . . . . . . . . . . . . . . . . . . . . . . . see figure 1 and 2 symbol parameter max units conditions c in input capacitance 7 pf v = 0 to 3v c out output capacitance 7 pf v = 0 to 3v figure 1 : ac output loading 577 ohms 30 pf 789 ohms 3.0v including scope and output fixture figure 2 : ac output loading for tristate specs (t hz , t lz , t wlqz , t whqz , t glqx , t ghqz ) 577 ohms 5 pf 789 ohms 3.0v including scope and output fixture
6 simtek confidential jan, 2008 document control #ml0061 rev 1.1 STK14EC16 preliminary sram read cycles #1 & #2 note c: w must be high during sram read cycles. note d: device is continuously selected with e and g both low, lb and ub select bytes read. note e: measured 200mv from steady state output voltage. note f: hsb must remain high during read and write cycles. sram read cycle #1: address controlled c,d,f sram read cycle #2: e and g controlled c,f no. symbols parameter STK14EC16-15 STK14EC16-25 STK14EC16-45 units #1 #2 alt. min max min max min max 1 t elqv t acs chip enable access time 15 25 45 ns 2 t avav c t eleh c t rc read cycle time 15 25 45 ns 3 t avqv d t avqv d t aa address access time 15 25 45 ns 4 t glqv t oe output enable to data valid 10 12 20 ns 5 t blqv byte enable to data valid 10 12 20 ns 6 t axqx d t axqx d t oh output hold after address change 3 3 3 ns 7 t elqx t lz address change or chip enable to output active 3 3 3 ns 8 t ehqz e t hz address change or chip disable to output inactive 7 10 15 ns 9 t blqx byte enable to output active 7 10 15 ns 10 t glqx t olz output enable to output active 0 0 0 ns 11 t ghqz e t ohz output disable to output inactive 7 10 15 ns 12 t bhqz e byte enable to output inactive 7 10 15 ns 13 t elicch b t pa chip enable to power active 0 0 0 ns 14 t ehiccl b t ps chip disable to power standby 15 25 45 ns previous data valid output data valid address valid (3) (6) address data output t avav t avqv t axqx (2) 6 t elq x stand by data val id 4 t glqv dq (d ata o ut ) e addr ess g i cc ac tive 10 t eli cc h 11 t ehi cc l 7 t ehq z 8 t glqx 1 t el q v 9 t gh q z 2 t eleh 29 t ehax 3 t av q v 27
STK14EC16 7 simtek confidential jan, 2008 document control #ml0061 rev 1.1 preliminary sram write cycles #1, #2, and #3 note g: if w is low when e goes low, the outputs remain in the high-impedance state. note h: e or w must be v ih during address transitions. sram write cycle #1: w controlled g,h sram write cycle #2: e controlled g,h no. symbols parameter STK14EC16-15 STK14EC16-25 STK14EC16-45 units #1 #2 #3 alt. min max min max min max 15 t avav t avav t avav t wc write cycle time 15 25 45 ns 16 t wlwh t wleh t wlbh t wp write pulse width 10 20 30 ns 17 t elwh t eleh t elbh t cw chip enable to end of write 15 20 30 ns 18 t blwh t bleh t blbh byte enable to end of write 15 20 30 ns 19 t dvwh t dveh t dvbh t dw data set-up to end of write 5 10 15 ns 20 t whdx t ehdx t bhdx t dh data hold after end of write 0 0 0 ns 21 t avwh t aveh t avbh t aw address set-up to end of write 10 20 30 ns 22 t avwl t avel t avbl t as address set-up to start of write 0 0 0 ns 23 t whax t ehax t bhax t wr address hold after end of write 0 0 0 ns 24 t wlqz e, g t wz write enable to output disable 7 10 15 ns 25 t whqx t ow output active after end of write 3 3 3 ns address valid high impedance input data valid previous data t avav (15) t elwh (17) t blwh (18) t avwh (21) t wlwh (16) address data output data input e lb, ub w t avwl (22) t wlqz (24) t dvwh (19) t whqx (25) t whdx (20) t whax (23) input data valid high impedance address valid data input data output lb , ub w e address t avav (15) t avwl (22) t eleh (17) t ehax (23) t bleh (18) t wleh (16) t ehdx (20) t dveh (19)
8 simtek confidential jan, 2008 document control #ml0061 rev 1.1 STK14EC16 preliminary sram write cycle #3: l b , ub controlled g,h autostore ?/power-up recall note i: t hrecall starts from the time v cc rises above v switch note j: if an sram write has not taken place since the last nonvolatile cycle, no store will take place autostore ?/power-up recall no. symbols parameter STK14EC16 units notes standard alternate min max 26 t hrecall power-up recall duration 20 ms i 27 t store t hlhz store cycle duration 12.5 ms j 28 v switch low voltage trigger level 2.65 v 29 v ccrise v cc rise time 150 s input data valid t avbl t bhdx address e w data input data output t avav t blbh t bhax t wlbh t dvbh high impedance address valid t elbh lb , ub (15) (22) (17) (23) (18) (16) (19) (20) t avbh (21) t store (27) v cc v switch (28) t vccrise (29) t store (27) autostore power-up recall t hrecall (26) t hrecall (26) read & write inhibited power-up recall read & write brown out autostore power-up recall read & write power down autostore ** ** note: read and write cycles will be ignored during store, recall and while v cc is below v switch ** autostore occures only if at least one sram write has happened
STK14EC16 9 simtek confidential jan, 2008 document control #ml0061 rev 1.1 preliminary software-controlled store / recall cycle k.l note k: the software sequence is clocked on the falling edge of e controlled reads or g controlled reads note l: the six consecutive addresses must be read in the order listed in the software store/recall mode selection table. w must be high during all six consecutive e or g controlled cycles. software store / recall cycle: e controlled l software store / recall cycle: g controlled l no. symbols parameter STK14EC16-15 STK14EC16-25 STK14EC16-45 units notes e cont k g cont k alternate min max min max min max 30 t avav t avav t rc store / recall initiation cycle time 15 25 45 ns 31 t avel t avgl t as address set-up time 0 0 0 ns 32 t eleh t glgh t cw clock pulse width 12 20 30 ns 33 t ehax t ghax address hold time 1 1 1 ns l 34 t recall t recall recall duration 150 150 150 s dq (data) g e 30 t avav data valid address address #1 high impedence 31 t avel 33 t ehax 32 t eleh 34 t recall 30 t avav address #6 27 t store data valid / deby address e g dq (data) 30 t avav data valid address #1 high impedence 34 t recall 30 t avav address #6 27 t store 31 t avgl 32 t glgh data valid / 33 t ghax pachuco boys
10 simtek confidential jan, 2008 document control #ml0061 rev 1.1 STK14EC16 preliminary hardware store cycle note m: on a hardware store initiation, sram operation continues to be enabled for time t delay to allow read/write cycles to complete hardware store cycle symbols parameter STK14EC16 units notes standard alternate min max 35 t delay t hlqz hardware store to sram disabled 1 70 s m 36 t hlhx hardware store pulse width 15 ns hsb (out) hsb (in) dq (data out) 35 t delay sram enabled 36 t hlhx sram enabled 27 t store soft sequence commands note n: this is the amount of time that it takes to take action on a soft sequence command. vcc power must remain high to effect ively register com - mand. note o: commands like store and recall lock out i/o until operation is complete which further increases this time. see specific command. no. symbols parameter STK14EC16 units notes standard min max 37 t ss soft sequence processing time 70 s n,o soft sequence command soft sequence command address #1 address #6 address #1 address #6 address vcc t ss 33 t ss 33
STK14EC16 11 simtek confidential jan, 2008 document control #ml0061 rev 1.1 preliminary mode selection e w g , ub , lb a 17 -a 0 mode i/o power notes h x x x not selected output high z standby l h l x read sram output data active l l x x write sram input data active l h l 0x04e38 0x0b1c7 0x083e0 0x07c1f 0x0703f 0x08b45 read sram read sram read sram read sram read sram autostore disable output data output data output data output data output data output data active p,q,r l h l 0x04e38 0x0b1c7 0x083e0 0x07c1f 0x0703f 0x04b46 read sram read sram read sram read sram read sram autostore enable output data output data output data output data output data output data active p,q,r l h l 0x04e38 0x0b1c7 0x083e0 0x07c1f 0x0703f read sram read sram read sram read sram read sram output data output data output data output data output data active p,q,r 0x08fc0 nonvolatile store output high z i cc2 l h l 0x04e38 0x0b1c7 0x083e0 0x07c1f 0x0703f 0x04c63 read sram read sram read sram read sram read sram nonvolatile recall output data output data output data output data output data output high z active p,q,r note p: the six consecutive addresses must be in the order listed. w must be high during all six consecutive cycles to enable a nonvolatile cycle. note q: while there are 18 addresses on the STK14EC16, only the lower 16 are used to control software modes note r: i/o state depends on the state of g, ub , and lb . the i/o table shown assumes g , ub , and lb low.
12 simtek confidential jan, 2008 document control #ml0061 rev 1.1 STK14EC16 preliminary nvsram the STK14EC16 nvsram is made up of two func - tional components paired in the same physical cell. these are the sram memory cell and a nonvolatile quantumtrap cell. the sram memory cell operates like a standard fast static ram. data in the sram can be transferred to the nonvolatile cell (the store operation), or from the nonvolatile cell to sram (the recall operation). this unique archi - tecture allows all cells to be stored and recalled in parallel. during the store and recall operations sram read and write operations are inhibited. the STK14EC16 supports unlimited read and writes like a typical sram. in addition, it provides unlimited recall operations from the nonvolatile cells and up to 200k store operations. sram read the STK14EC16 performs a read cycle whenever e and g are low while w and hsb are high. the address specified on pins a 0-17 determine which of the 262,144 data words will be accessed. byte enables ( ub , lb ) determine which bytes are enabled to the output. when the read is initiated by an address transition, the outputs will be valid after a delay of t avqv (read cycle #1). if the read is initiated by e and g , the outputs will be valid at t elqv or at t glqv , whichever is later (read cycle #2). the data outputs will repeatedly respond to address changes within the t avqv access time with - out the need for transitions on any control input pins, and will remain valid until another address change or until e or g is brought high, or w and hsb is brought low. sram write a write cycle is performed whenever e and w are low and hsb is high. the address inputs must be stable prior to entering the write cycle and must remain stable until either e or w goes high at the end of the cycle. the data on the common i/o pins dq0-15 will be written into memory if it is valid t dvwh before the end of a w controlled write or t dveh before the end of an e controlled write. the byte enable inputs ( ub , lb ) determine which bytes are written. it is recommended that g be kept high during the entire write cycle to avoid data bus contention on common i/o lines. if g is left low, internal circuitry will turn off the output buffers t wlqz after w goes low. autostore operation the STK14EC16 stores data to nvsram using one of three storage operations. these three operations are hardware store (activated by hsb), software store (activated by an address sequence), and autostore (on power down). autostore operation is a unique feature of simtek quantum trap technology that is enabled by default on the STK14EC16. during normal operation, the device will draw cur - rent from v cc to charge a capacitor connected to the v cap pin. this stored charge will be used by the chip to perform a single store operation. if the voltage on the v cc pin drops below v switch , the part will automatically disconnect the v cap pin from v cc . a store operation will be initiated with power provided by the v cap capacitor. figure 3 shows the proper connection of the storage capacitor (v cap ) for automatic store operation. refer to the dc characteristics table for the size of the capacitor. the voltage on the v cap pin is driven to 3.6v by a regulator on the chip. a pull up should be placed on w to hold it inactive during power up. this pull-up is only effective if the w signal figure 3. autostore mode v cap v cc w 10k ohm 0.1f v cc v cap nvsram operation
STK14EC16 13 simtek confidential jan, 2008 document control #ml0061 rev 1.1 preliminary is tri-state during power up. many mpu?s will tri-state their controls on power up. this should be verified when using the pullup. when the nvsram comes out on power-on-recall, the mpu must be active or the w held inactive until the mpu comes out of reset. to reduce unneeded nonvolatile stores, autostore and hardware store operations will be ignored unless at least one write operation has taken place since the most recent store or recall cycle. software initiated store cycles are per - formed regardless of whether a write operation has taken place. the hsb signal can be monitored by the system to detect an autostore cycle is in progress. hardware store ( hsb ) operation the STK14EC16 provides the hsb pin for control - ling and acknowledging the store operations. the hsb pin can be used to request a hardware store cycle. when the hsb pin is driven low, the stk14ec8 will conditionally initiate a store oper - ation after t delay . an actual store cycle will only begin if a write to the sram took place since the last store or recall cycle. the hsb pin has a very resistive pullup and is internally driven low to indicate a busy condition while the store (initiated by any means) is in progress. this pin should be externally pulled up if it is used to drive other inputs. sram read and write operations that are in progress when hsb is driven low by any means are given time to complete before the store operation is initiated. after hsb goes low, the STK14EC16 will continue to allow sram operations for t delay . dur - ing t delay , multiple sram read operations may take place. if a write is in progress when hsb is pulled low, it will be allowed a time, t delay , to com - plete. however, any sram write cycles requested after hsb goes low will be inhibited until hsb returns high. if hsb is not used, it should be left unconnected. hardware recall (power-up) during power up or after any low-power condition (v cc STK14EC16 software store cycle is initiated by executing sequential e controlled or g controlled read cycles from six specific address locations in exact order. during the store cycle, previous data is erased and then the new data is programmed into the nonvolatile elements. once a store cycle is initiated, further memory inputs and outputs are dis - abled until the cycle is completed. to initiate the software store cycle, the following read sequence must be performed: once the sixth address in the sequence has been entered, the store cycle will commence and the chip will be disabled. it is important that read cycles and not write cycles be used in the sequence and that g , ub , and lb are active. after the t store cycle time has been fulfilled, the sram will again be activated for read and write opera - tion. software recall data can be transferred from the nonvolatile mem - ory to the sram by a software address sequence. a software recall cycle is initiated with a sequence of read operations in a manner similar to the soft - ware store initiation. to initiate the recall cycle, the following sequence of e controlled or g controlled read operations must be performed: internally, recall is a two-step procedure. first, the sram data is cleared, and second, the nonvola - tile information is transferred into the sram cells. 1 read address 0x4e38 valid read 2 read address 0xb1c7 valid read 3 read address 0x83e0 valid read 4 read address 0x7c1f valid read 5 read address 0x703f valid read 6 read address 0x8fc0 initiate store cycle 1 read address 0x4e38 valid read 2 read address 0xb1c7 valid read 3 read address 0x83e0 valid read 4 read address 0x7c1f valid read 5 read address 0x703f valid read 6 read address 0x4c63 initiate recall cycle
14 simtek confidential jan, 2008 document control #ml0061 rev 1.1 STK14EC16 preliminary after the t recall cycle time, the sram will once again be ready for read or write operations. the recall operation in no way alters the data in the nonvolatile storage elements.care must be taken so the controlling falling edge is glitch and ring free so as not to double clock the read address. data protection the STK14EC16 protects data from corruption dur - ing low-voltage conditions by inhibiting all externally initiated store and write operations. the low- voltage condition is detected when v cc STK14EC16 is in a write mode (both e and w low) at power-up, after a recall, or after a store, the write will be inhibited until a negative transition on e or w is detected. this protects against inadvertent writes during power up or brown out conditions. noise considerations the STK14EC16 is a high-speed memory and so must have a high-frequency bypass capacitor of 0.1 f connected between both v cc pins and v ss ground plane with no plane break to chip v ss . use leads and traces that are as short as possible. as with all high-speed cmos ics, careful routing of power, ground, and signals will reduce circuit noise. best practices nvsram products have been used effectively for over 15 years. while ease-of-use is one of the prod - uct?s main system values, experience gained work - ing with hundreds of applications has resulted in the following suggestions as best practices: ? the non-volatile cells in this nvsram product are delivered from simtek with 0x00 written in all cells. incoming inspection routines at customer or contract manufacturer?s sites will sometimes reprogram these values. final nv patterns are typically complex 4-byte pattern of 46 e6 49 53 hex or more random bytes. end product?s firm - ware should not assume an nv array is in a set programmed state. routines that check memory content values to determine first time system con - figuration, cold or warm boot status, etc. should always program a unique nv pattern (i.e., repeat - ing 4-byte pattern of 46 e6 49 53 hex) as part of the final system manufacturing test to ensure these system routines work consistently. ? power up boot firmware routines should rewrite the nvsram into the desired state (autostore enabled, etc.). while the nvsram is shipped in a preset state, best practice is to again rewrite the nvsram into the desired state as a safeguard against events that might flip the bit inadvertently (program bugs, incoming inspection routines, etc.). ? the autostore enabled/disabled feature will reset to ?autostore enabled? on every power down event captured by the nvsram. the application firmware should disable autostore on each reset sequence that this behavior is desired. ? the v cap value specified in this datasheet includes a minimum and a maximum value size. best practice is to meet this requirement and not exceed the max v cap value because the nvsram internal algorithm calculates v cap charge time based on this max vcap value. customers that want to use a larger v cap value to make sure there is extra store charge and store time should discuss their v cap size selection with simtek to understand any impact on the v cap voltage level at the end of a t recall period. low average active power cmos technology provides the STK14EC16 with the benefit of power supply current that scales with cycle time. less current will be drawn as the mem - ory cycle time becomes longer than 50 ns. figure 4 shows the relationship between i cc and read/ write cycle time. worst-case current consumption is shown for commercial temperature range, v cc =3.6v, and chip enable at maximum frequency. only standby current is drawn when the chip is dis - abled. the overall average current drawn by the STK14EC16 depends on the following items: 1 the duty cycle of chip enable 2 the overall cycle rate for operations 3 the ratio of reads to writes 4 the operating temperature 5 the v cc level 6 i/o loading
STK14EC16 15 simtek confidential jan, 2008 document control #ml0061 rev 1.1 preliminary preventing autostore the autostore function can be disabled by initiating an autostore disable sequence. a sequence of read operations is performed in a manner similar to the software store initiation. to initiate the autostore disable sequence, the following sequence of e controlled or g controlled read operations must be performed: the autostore can be re-enabled by initiating an autostore enable sequence. a sequence of read operations is performed in a manner similar to the software recall initiation. to initiate the autostore enable sequence, the following sequence of e controlled or g controlled read operations must be performed: if the autostore function is disabled or re-enabled, a manual store operation (hardware or soft- ware) needs to be issued to save the autostore state through subsequent power down cycles. the part comes from the factory with autostore enabled, but best design practice is to set the enable or disable state during each power-up sequence and not depend on this factory default condition. simtek recommends users configure the part completely for the specific application. 1 read address 0x4e38 valid read 2 read address 0xb1c7 valid read 3 read address 0x83e0 valid read 4 read address 0x7c1f valid read 5 read address 0x703f valid read 6 read address 0x8b45 autostore disable 1 read address 0x4e38 valid read 2 read address 0xb1c7 valid read 3 read address 0x83e0 valid read 4 read address 0x7c1f valid read 5 read address 0x703f valid read 6 read address 0x4b46 autostore enable figure 4 - current vs cycle time
16 simtek confidential jan, 2008 document control #ml0061 rev 1.1 STK14EC16 preliminary ordering information STK14EC16-t f 45 i tr packing option blank = tube tr = tape and reel temperature range blank = commercial (0 to +70 c) i = industrial (-40 to +85 c) access time 15 = 15 ns 25 = 25 ns 45 = 45 ns lead finish f = nickel/palladium/gold (ni/pd/au) package t = plastic 44-pin 400 mil tsopii (32 mil pitch) u = plastic 54-pin 400 mil tsopii (32 mil pitch) b = plastic 48-pin fbga (fine pitch ball grid array)
STK14EC16 17 simtek confidential jan, 2008 document control #ml0061 rev 1.1 preliminary ordering codes part number description a ccess times temperature 2tk14ec16-tf15 3v 4m-16b autostore nvsram tsop44-400 15 ns access time commercial STK14EC16-tf15tr 3v 4m-16b autostore nvsram tsop44-400 15 ns access time commercial STK14EC16-tf25 3v 4m-16b autostore nvsram tsop44-400 25 ns access time commercial STK14EC16-tf25tr 3v 4m-16b autostore nvsram tsop44-400 25 ns access time commercial STK14EC16-tf45 3v 4m-16b autostore nvsram tsop44-400 45 ns access time commercial STK14EC16-tf45tr 3v 4m-16b autostore nvsram tsop44-400 45 ns access time commercial STK14EC16-uf15 3v 4m-16b autostore nvsram tsop54-400 15 ns access time commercial STK14EC16-uf15tr 3v 4m-16b autostore nvsram tsop54-400 15 ns access time commercial STK14EC16-uf25 3v 4m-16b autostore nvsram tsop54-400 25 ns access time commercial STK14EC16-uf25tr 3v 4m-16b autostore nvsram tsop54-400 25 ns access time commercial STK14EC16-uf45 3v 4m-16b autostore nvsram tsop54-400 45 ns access time commercial STK14EC16-uf45tr 3v 4m-16b autostore nvsram tsop54-400 45 ns access time commercial STK14EC16-bf15 3v 4m-16b autostore nvsram fbga48 15 ns access time commercial STK14EC16-bf15tr 3v 4m-16b autostore nvsram fbga48 15 ns access time commercial STK14EC16-bf25 3v 4m-16b autostore nvsram fbga48 25 ns access time commercial STK14EC16-bf25tr 3v 4m-16b autostore nvsram fbga48 25 ns access time commercial STK14EC16-bf45 3v 4m-16b autostore nvsram fbga48 45 ns access time commercial STK14EC16-bf45tr 3v 4m-16b autostore nvsram fbga48 45 ns access time commercial STK14EC16-tf15i 3v 4m-16b autostore nvsram tsop44-400 15 ns access time industrial STK14EC16-tf15itr 3v 4m-16b autostore nvsram tsop44-400 15 ns access time industrial STK14EC16-tf25i 3v 4m-16b autostore nvsram tsop44-400 25 ns access time industrial STK14EC16-tf25itr 3v 4m-16b autostore nvsram tsop44-400 25 ns access time industrial STK14EC16-tf45i 3v 4m-16b autostore nvsram tsop44-400 45 ns access time industrial STK14EC16-tf45itr 3v 4m-16b autostore nvsram tsop44-400 45 ns access time industrial STK14EC16-uf15i 3v 4m-16b autostore nvsram tsop54-400 15 ns access time industrial STK14EC16-uf15itr 3v 4m-16b autostore nvsram tsop54-400 15 ns access time industrial STK14EC16-uf25i 3v 4m-16b autostore nvsram tsop54-400 25 ns access time industrial STK14EC16-uf25itr 3v 4m-16b autostore nvsram tsop54-400 25 ns access time industrial STK14EC16-uf45i 3v 4m-16b autostore nvsram tsop54-400 45 ns access time industrial STK14EC16-uf45itr 3v 4m-16b autostore nvsram tsop54-400 45 ns access time industrial STK14EC16-bf15i 3v 4m-16b autostore nvsram fbga48 15 ns access time industrial STK14EC16-bf15itr 3v 4m-16b autostore nvsram fbga48 15 ns access time industrial STK14EC16-bf25i 3v 4m-16b autostore nvsram fbga48 25 ns access time industrial STK14EC16-bf25itr 3v 4m-16b autostore nvsram fbga48 25 ns access time industrial STK14EC16-bf45i 3v 4m-16b autostore nvsram fbga48 45 ns access time industrial STK14EC16-bf45itr 3v 4m-16b autostore nvsram fbga48 45 ns access time industrial
18 simtek confidential jan, 2008 document control #ml0061 rev 1.1 STK14EC16 preliminary package diagrams 54-pin tsopii 5 0 0.0235 0.597 0.0160 0.406 0.396 10.058 0.404 10.262 0.047 1.194 0.039 0.991 0.016 0.400 0.012 0.300 ( ) 0.0315 (0.800) bsc 0.729 18.517 0.721 18.313 ( ) 0.150 0.0059 0.050 0.0020 base plane seating plane 0.004 (0.10) dim = inches dim = mm min max min max 1 27 28 54 pin 1 index top view ( ) 0.404 0.396 10.262 10.058 ( ) 0.470 0.462 11.938 11.735 ( 0.878 0.886 22.517 22.313 ) ( ) ) ( ) ( ) ( ) (
STK14EC16 19 simtek confidential jan, 2008 document control #ml0061 rev 1.1 preliminary 44-pin tsopii 5 0 0.0235 0.597 0.0160 0.406 0.396 10.058 0.404 10.262 0.047 1.194 0.039 0.991 0.016 0.400 0.012 0.300 0.0315 (0.800) bsc 0.729 18.517 0.721 18.313 0.050 0.0020 base plane seating plane 0.004 (0.10) dim = inches dim = mm min max min max 0.404 0.396 10.262 10.058 0.470 0.455 11.938 11.735 top view 22 23 44 1 pin 1 index ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( 0.150 0.0059
20 simtek confidential jan, 2008 document control #ml0061 rev 1.1 STK14EC16 preliminary 48-ball fbga a b c d e f g h a b c d e f g h 6 5 4 3 2 1 1.875 0.75 3.75 6.00 0.10 b 2.625 0.75 5.25 10.00 0.10 a 0.15(4x) 1 2 3 4 5 6 a1 corner a1 corner 10.00 0.10 a 6.00 0.10 b 0.15c 0.25c // 0.53 0.05 0.21 0.05 seating plane c 0.36 120 max ?0.05 m c ?0.25 m ca b 00.30 0.05(48x) top view bottom view + ++ + +
STK14EC16 21 simtek confidential jan, 2008 document control #ml0061 rev 1.1 preliminary document revision history rev date change 1.0 april 2007 moved to preliminary from advance information ? made clear that nominal supply is 3.3v, not 3.0v (range 2.7v to 3.6v) ? modified language on pin description of hsb and nc. ? changed isb from 1ma to 2ma. ? changed icc3 from 8ma to 26ma ? clarified description language of figure 3 ? clarified description language of software recall ? clarified description language of preventing autostore ? corrected typo on industrial temp range: -45 to -40 1.1 january 2008 made the following changes to the document ? page 1: revised block diagram ? page 3: added new 48 fbga information, bock diagram, and package diagram; added pin descriptions for pins e , lb , ub , and w . ? page 4: added thermal characteristics. in the dc characteristics table, revised values for i cc2 , i cc4 , i sb , v ih , and v cap ;and changed industrial max value of v cap to 180 and revised v cap notes. added ?(except hsb )? to notes for output logic ?1? voltage. ? page 6: in sram read cycles #1 & #2 table, revised description for t elqx and t ehqz and changed symbol #2 to t eleh for read cycle time; updated sram read cycle #2 timing diagramand changed title to add g controlled. ? page 7: in sram write cycles, added symbol #3. ? page 8: added new sram write cycle #3. in autostore/power-up recall table, changed max value for #27 (t store ) to 12.5. revised autostore/power-up recall section. ? page 9: in software-controlled store/recall cycle table, revised values for t recall ; revised the notes below the software-controlled store/recall cycle diagram. ? page 11: in mode selection table, changed column to a 17 -a 0 . in the values in this column, added a zero after each instance of ?0x?; changed autostore enable value to 0x04b46. ? page 12: in auto-store operation, deleted line about v cap pin being driven to 5v by a charge pump internal to the chip. also, added stefan's revised text (italics show revision): "refer to the dc characteristics table for the size of the capacitor." ? page 13: under hardware store (hsb ) operation, revised first paragraph to read ?the hsb pin has a very resistive pullup...? ? page 14: added best practices section. ? page 16: in ordering information, lead finish, replaced ?sn (matte tin) rohs compliant? with ?nickel/palladium/gold (ni/pd/au).? also, added ?b = plastic 48-pin fbga (fine pitch ball grid array)? to finish. ? page 17: in ordering codes, added ordering information for 48 fbga and added access times column.

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